Micro electrical impedance tomography on a single CMOS chip

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A time-domain band-gap temperature sensor in SOI CMOS for higherature applications

10.1109/TCSII.2014.2386231IEEE Transactions on Circuits and Systems II: Express Briefs625436-44

A 65-nm 8T SRAM compute-in-memory macro with column ADCs for processing neural networks

In this work, we present a novel 8T static random access memory (SRAM)-based compute-in-memory (CIM) macro for processing neural networks with high energy efficiency. The proposed 8T bitcell is free from disturb issues thanks to the decoupled read channels by adding two extra transistors to the standard 6T bitcell. A 128 $\times$ 128 8T SRAM array offers massively parallel binary multiply and accumulate (MAC) operations with 64 $\times$ binary inputs (0/1) and 64 $\times$ 128 binary weights (+1/-1). After parallel MAC operations, 128 column-based neurons generate 128 $\times$ 1-5 bit outputs in parallel. The proposed column-based neuron comprises 64 $\times$ bitcells for dot-product, 32 $\times$ bitcells for analog-to-digital converter (ADC), and 32 $\times$ bitcells for offset calibration. The column ADC with 32 $\times$ replica SRAM bitcells converts the analog MAC results (i.e., a differential read bitline (RBL/RBLb) voltage) to the 1-5 bit output code by sweeping their reference levels in 1-31 cycles (i.e., $2^{N}$ -1 cycles for $N$ -bit ADC). The measured linearity results [differential nonlinearity (DNL) and integral nonlinearity (INL)] are +0.314/-0.256 least significant bit (LSB) and + 0.27/-0.116 LSB, respectively, after offset calibration. The simulated image classification results are 96.37% for Mixed National Institute of Standards and Technology database (MNIST) using a multi-layer perceptron (MLP) with two hidden layers, 87.1%/82.66% for CIFAR-10 using VGG-like/ResNet-18 convolutional neural networks (CNNs), demonstrating slight accuracy degradations (0.67%-1.34%) compared with the software baseline. A test chip with a 16K 8T SRAM bitcell array is fabricated using a 65-nm process. The measured energy efficiency is 490-15.8 TOPS/W for 1-5 bit ADC resolution using 0.45-/0.8-V core supply.Agency for Science, Technology and Research (A*STAR)This work was supported by the Agency for Science, Technology and Research (A*STAR), Singapore, under Grant A18A7b0058

A time-domain wavefront computing accelerator with a 32 × 32 reconfigurable PE array

This work presents a hardware accelerator realizing true time-domain wavefront computing in a massive parallel two-dimensional (2-D) processing element (PE) array. The proposed 2-D time-domain PE array is designed for multiple applications based on its scalable and reconfigurable architecture. The shortest path problem (a classical problem in graph theory) is one of the critical problems to solve using the proposed accelerator. Unlike the A∗ search algorithm, a heuristic method widely used in shortest path searching problems, the proposed accelerator requires only the propagation of rising-edge signals through the PE array without calculating or estimating the distances from the start to the goal. Hence, a single execution of the proposed time-domain wavefront computing provides all the optimal paths from a start point to an arbitrary goal. Besides the King's graph model used for solving the shortest path searching, the PE array is reconfigured to a simpler lattice graph model and solves other problems, such as maze solving we used in this article as a benchmark. In addition, we used the proposed accelerator to demonstrate a scientific simulation. The propagation of circular or planar wavefronts was simulated using single or multiple start points using King's graph configuration. A 1 × 1 mm2 test chip with a 32 × 32 reconfigurable time-domain PE array is fabricated using a 65-nm process. For a 2-D map with 32 × 32 vertices, the proposed PE array consumes 776 pJ per task and achieves 1.6 G edges/second search rate using 1.2-/1.0-V core supply voltages.Agency for Science, Technology and Research (A*STAR)This work was supported by the A∗STAR RIE2020 Advanced Manufacturing and Engineering (AME) Programmatic Fund under Grant A19E8b0102

Dual mode acoustic wave sensor for precise pressure reading

In this letter, a Microelectromechanical system acoustic wave sensor, which has a dual mode (lateral field exited Lamb wave mode and surface acoustic wave (SAW) mode) behavior, is presented for precious pressure change read out. Comb-like interdigital structured electrodes on top of piezoelectric material aluminium nitride (AlN) are used to generate the wave modes. The sensor membrane consists of single crystalline silicon formed by backside-etching of the bulk material of a silicon on insulator wafer having variable device thickness layer (5 μm–50 μm). With this principle, a pressure sensor has been fabricated and mounted on a pressure test package with pressure applied to the backside of the membrane within a range of 0 psi to 300 psi. The temperature coefficient of frequency was experimentally measured in the temperature range of −50 °C to 300 °C. This idea demonstrates a piezoelectric based sensor having two modes SAW/Lamb wave for direct physical parameter—pressure readout and temperature cancellation which can operate in harsh environment such as oil and gas exploration, automobile and aeronautic applications using the dual mode behavior of the sensor and differential readout at the same time.ASTAR (Agency for Sci., Tech. and Research, S’pore)Published versio